The present disclosure herein relates to a memory device, and more particularly, to an error location search circuit used in a memory device, and an error check and correction circuit and a memory device including the same.
NAND flash memory is one example of electrically erasable and programmable read only memory (EEPROM), there is a. A NAND flash memory may store large amounts of information in a small chip area by using NAND cell units where a plurality of memory cells are connected in series to each other.
In the case of a large capacity memory such as a NAND flash memory, a memory cell may lose its storage characteristics due to the deterioration of a tunnel oxide layer after several program operations. For example, while data is stored in a NAND flash memory, stored data may be damaged due to various causes. Therefore, an error rate may increase. Especially, as memory capacity is increased drastically and manufacturing processes become more complex, an error rate may increase. In order to solve the above issues and improve the performance of a flash memory, an error correction code (ECC) circuit is being used. If an ECC system is mounted in a chip, highly-reliable memory may be obtained. Furthermore, after redundant data of error correction code are added to data to be stored, the data are programmed as data strings. Additionally, when data is read, erroneous data is corrected with the redundant data of the error correction code.
Meanwhile, since data cannot be outputted to the outside of a memory until a correction operation of an ECC system is completed, it is necessary to reduce a time for completing the correction operation. For this, the use of the Hamming code which is capable of fast processing is studied. Also, a way for making the BCH (Bose-Chaudhuri-Hocquenghem) code which is capable of performing corrections of high orders be fast is being studied. The BCH code is one of block codes using a Galois Field operation. According to a block code such as the BCH code and the Reed-Solomon code, an error location may be calculated by using an error locator polynomial. For example, error location search is performed by calculating the roots of the polynomial after subsequently substituting each element, which is not 0, of the Galois Field into the error locator polynomial. This root search process is called Chien search. There are related art methods for increasing the speed of the Chien search, and related art methods for forming a NAND flash memory including an ECC circuit.
According to related art methods for increasing the speed of the Chien search, a configuration of a Chien search circuit indicating an error locator polynomial may use flip-flops, registers, and Galois field multiplication circuits. According to related art methods for increasing the speed of the Chien search, signals indicating bit positions are provided to the Chien search circuit and it is determined whether there is an error in a corresponding bit. In this case, a plurality of Chien search circuits may be equipped to determine whether there are errors in a plurality of bits in parallel.
According to related art methods for increasing the speed of the Chien search, as the number of bits processed in parallel is increased, the number of Chien search circuits is increased. Also, as the number of Chien search circuits is increased, the number of lines for providing signals that represents bit positions to the Chien search circuit is increased. Accordingly, as the number of bits processed in parallel is increased, scale of a Chien search unit including Chien search circuits and peripheral circuits is increased.
According to related art methods for forming a NAND flash memory including an ECC circuit, the ECC circuit substitutes bit positions of data strings into the error locator polynomial by a Chien Search unit and detects whether there is an error in a corresponding bit. When a data string is outputted, an address is substituted, from the lowest bit to the highest bit, into the Chien Search unit. Moreover, the ECC circuit corrects the data having error bits to output the corrected data, or outputs the data having no error bit as they are.
According to related art methods for forming a NAND flash memory including an ECC circuit, in order to read a bit of an arbitrary position in a data string, a bit outputted from the ECC circuit is stored in a buffer memory first, and then an address of a bit to be read is provided to the buffer memory. For example, until the ECC circuit corrects all data having error bits with respect to all bits of a data string including a bit to be read, it may be impossible to read the corrected data at high speed.
In order to output the corrected data to the outside of a memory at high speed, data having error bits in all bits of a data string including a bit to be read need to be corrected at high speed. In order to correct the data having an error bit at high speed, a method of simultaneously substituting address values from the lowest bit to the highest bit into the Chien search unit may be used. In order to use this method, the Chien search unit of the ECC circuit may need to include a position search circuit substituting bit positions into the error locator polynomial. In this case, the position search circuit may need to be equipped to correspond to each bit.
FIG. 26 is a block diagram illustrating a configuration of a Chien search unit 339 according to the related art. For example, it is assumed that the Chien search unit 339 uses a Galois Field GF(29). Additionally, it is assumed that an ECC circuit using the BCH code to correct 4-bit errors is included. For example, on the basis of the Galois Field GF(29), errors of 4-bit among 511-bit may be corrected. Although described later in detail, when 511-bit are simultaneously corrected through the Chien search unit 339 according to the related art under the above assumption, a total of 353612 logic circuits are required.